Code converter with provision for automatically generating precedence codes



May 9, 1967 GRYK 3,319,244 CODE CONVERTER WITH PROVISION FORAUTOMATICALLY GENERATING, PRECEDENCE CODES Original Filed March 4, 19642 Sheets-Sheet 1 FIGS.

INVENTOR ATTORNEYS L. GRYK 3,319,244 CODE CONVERTER WITH PROVISION FORAUTOMATICALLY May 9, 1967 GENERATING PRECEDENCE CODES Original FiledMarch 4, 1964 2 Sheets-Sheet 2 wuzmomummm umE United States Patent()fifice 3 ,319,244 Patented May 9, 1967 3 319,244 CODE CONVERTER {VlTHPROVISION FOR AU- lOMATllCALLY GENERATING PRECEDENCE CODES Leon Gryk,New Britain, Coum, assignor to Royal Typewriter Company, Inc., New York,N.Y., a corporation of Delaware Continuation of application Ser. No.349,253, Mar. 4, 1964. This application Nov. 16, 1966, Ser. No. 596,717

4 Claims. (Cl. 340-347) characters. For example, codes following one ofthe prece-v dence codes might represent lower case information on atypewriter keyboard and the same codes following the other precedencecode might represent upper case infor mation on the typewriter keyboard.The difiiculty in providing apparatus for converting first system codesto second system codes, aside from the fact that many systems do notemploy the same code assignment for a particular character, resides inthe fact that lower case information in one system is likely to be uppercase information in another system. Systems for converting first systemcodes to second system codes heretofore advanced accommodate the abovedifficulty only with complex and expensive circuitry.

In accordance with the present invention the above difficulty isaccommodate by simple and inexpensive apparatus which permits of theconversions of codes of any one system to codes of any one of severalother systems by the simple expedient of changing records on which firstsystem codes to be converted and corresponding codes of a second systemto which the first system codes are to be converted are prerecorded.

Broadly in accordance with the invention circuitry is provided tocompare input and prerecorded first system codes, to sense and storeduring coincidence of input and prerecorded first system codes theprerecorded second system code corresponding to the coincident firstsystem code, to thereafter determine from the prerecorded medium theprecedence or case assignment of the stored second system code and togenerate a precedence code for reproduction if required and after aninterval sufiicient for reproduction of the precedence code, then toread out the stored second system code for reproduction.

An object of the invention is to provide a code to code converter withprovision for generating precedence codes in a facile manner.

Another object of the invention is in the provision of a code to codeconverted employing prerecorded records containing first system codes tobe converted and second system codes to which said first system codesare to be converted whereby any code system may be converted to anyother code system simply by changing records.

A further object of the invention is in the provision of a code to codeconverter whereby any code system may be converted to any other codesystem at high speeds.

A further object of the invention is to provide a code to code converterwhich is capable of converting first system codes to second system codeswherein character code assignments as well as upper and lower casecharacter assignments differ.

A still further object of the invention is in the provision of a code tocode converter employing first and second endless records havingprerecorded thereon codes to be converted and codes to which said firstcodes are to be converted respectively, said second record containingprerecorded precedence information.

Still another object of the invention is in the provision of a code tocode converter wherein coincidence of input and prerecorded first systemcodes enable the readout of corresponding prerecorded second systemcodes and the generation of second system precedence codes Wherenecessary.

Other objects and many of the attendant advantages of this inventionwill be readily appreciated as the same becomes better understood byreference to the following detailed description when considered inconnection with the accompanying drawings in which like referencenumerals designate like parts throughout the figures thereof andwherein:

FIGURE 1 is a schematic block diagram of a code converter in accordancewith the invention employing two prerecorded discs; and

FIGURE 2 is a timing diagram explanatory of the operation of the FIGURE1 logic circuitry.

Referring now to the drawings wherein like reference charactersdesignate like or corresponding elements throughout the several viewsthere is shown in FIGURE 1 disc records A and B. The discs are adaptedto be synchronously driven, and to this end they may be mounted inaxially spaced relation on a motor driven shaft 2; the shaft beingprovided with a spline 3 and the discs with complementary keywayswhereby the disc are driven in fixed orientation relative to oneanother.

Disc A has recorded therein, as by perforating along radial lines,parallel bit code patterns 4 representing all the characters of and inaccordance with a first system code assignment. The bits of the codepatterns are recorded in parallel circular tracks designated 2- Due tothe fact that identical code patterns are, in most systems, employed torepresent two different characters, i.e. an upper and lower casecharacter, and are distinguishable by type basket operating caseprecedence or letters and figures precedence codes, in order torepresent all of the first system characters requires that each dualmeaning first system code be recorded twice in the disc A. In accordancewith the invention identical code patterns recorded on the disc A aredistinguishable by the presence or absence of a hole accompanying thecode pattern recorded in a precedence or case designator track 5. Asviewed in FIGURE 1 upper case character representative or Figures codesare grouped in a sector 6 and identical lower case characterrepresentive or Letters codes in the remaining disc area, thereby tosimplify the recording of case precedence designator holes by permittinga peripheral portion 7 to be cut away from the upper case or Figuressector 6 of the disc. Machine function code pattern such as carriagereturn, space, etc., which have no case will be recorded in both Lettersand Figures sectors. This arrangement permits, as will hereinafterappear, the problem of the ambiguity of identical first system codepatterns to be resolved.

Similarly disc B has recorded therein, as by perforating along radiallines, parallel bit code patterns 8 representing all the correspondingcharacters of and in accordance with a second system code assignment.

The code patterns 4 and 8 are recorded on the discs such that codepatterns representative of the same character have the same angularorientation relative to a reference such as the keyways. In a 5 to 8converter, the first system code patterns Will occupy bit tracks 2 2or1discAand2 2 0a discB.

In accordance with the invention the precedence or case assignment ofthe character represented by each code pattern on disc B regardless ofits precedence or case assignment in the first system code must bedeterminable. Accordingly, radial increments between code patterns 8have recorded therein precedence or case designator, holes 9 or 10,designating the case, upper or lower, of the character represented bythe code pattern preceding it. The precedence case-designator holes maybe recorded in discrete upper and lower case precedence track or asshown in the figure may be recorded in bit tracks e.g. tracks 2 and 2whereby transducers associated with these tracks may serve as precedencedetectors as well as bit detectors.

Associated with discs A and B are transducer assemblies 11 and 12respectively adapted to sense the perforated code patterns on the discs.

Transducer assemblies suitable for sensing hole patterns may compriselight sources on one side of the discs and light responsive cellsarrayed on the other side of the discs opposite each track. Thetransducer assemblies will be positioned such that each simultaneouslyreads a code on its corresponding disc representing the same chanacter.

In accordance with the invention code signal patterns of one system thatare to be converted and which are usually stored in a tape may besupplied to the code converter by a tape reader and corresponding secondsystem codes may be reproduced in a second tape by a record perforator Aconventional tape reader generally designated by reference numeral 13which responds to a true signal on a command line 14 may be employed inconjunction with the code converter of the invention. Signals will bedesignated true or false herein; the former being those which initiateor result from desired operation of a circuit element; the lattersignals being the opposite. True and false signals may be positive ornegative or vice versa. As will be understood by those conversant in theart a true signal on the command line 14 will cause the reader to cyclewhereby during the cycle code signal patterns will be issued to outputlines 15 and the record will be indexed.

The speed of the discs will be determined by the interval T (FIGURE 2)that code signal patterns are issued to output lines 15; the disc speedsbeing such that they make :a complete revolution during the interval Tthat code signal patterns are on lines 15.

The reader output lines 15 are connected to a comparator 16 as are theoutput lines 17 of AND gates 18. One leg of each of the AND gates isconnected to an associated light responsive cell input line 19 of thetransducer assembly 11 and the other legs of the AND gates 18 areconnected to the output of an OR gate 20 adapted to pass, as willhereinafter appear, a true signal only during the interval Figures codesare being sensed or only during intervals the Letters codes are beingsensed. Accordingly, if the reader issues to lines 15 an upper casecharacter representative code as determined by an issued precedingFigures code, when the transducer assembly 11 senses the identical codepattern in the Figures sector 6 of disc A a true signal will begenerated on the output line 21 of the comparator.

To determine which codes are to be compared i.e. first system Figures orLetters codes, the reader output lines 15 are connected to a letterscode detector 22 and a Figures code detector 23 which recognizes thesecodes and generate a true signal on their output lines which areconnected respectively to the set and reset terminals of a case memoryflip flop 24 whereby the leading edge of a Letters signal will set theflip flop and the leading edge of a subsequent Figures signal will resetthe flip flop. The two outputs of the flip flop are connectedrespectively to a Figures :and a Letters AND gate 25 and 26 whereby ifthe flip flop is set to theoutput to the Figures AND 4 gate 25 will befalse and the output to the Letters AND gate 26 will be true; theopposite obtaining when the flip flop is in reset state. The output line19P of the precedence or case designator track detecting cell of thetransducer assembly 11 is connected directly to the Figures AND gate 25and indirectly through an inverter I to the Letters AND gate 26.

If the flip flOp 24 is in an assumed Letters or set state, the LettersAND gate output will be true over the interval of time during which noopenings in the precedence or designator track 5 are being detected bythe precedence or designator detector cell of assembly 11. Similarly ifthe flop flop 24 is in an assumed Figures or reset state, the FiguresAND gate output will be true over the interval of time during whichopenings in the precedence or designator track 5 are being detected. Theoutputs of the case AND gates 25 and 26 are connected to the OR circuit20 whose output, as hereinbefore noted, conditions AND gates 18 to passbit signal patterns on lines 19 to the comparator for comparison withcode signal patterns on the reader output lines 15.

In view of the above it will be apparent that if the first code issuedby the reader is a Letters code the flip flop will, if not already in aset state, switch to set state. Accordingly, the Letters gate 26 will beconditioned to pass a Letters precedence signal and the Figures gate 25will be blocked to Figures precedence signals. Letters precedencesignals will be generated when no openings are detected in theprecedence or case track 5 and Figures precedence signals when openingsare detected. Only signal patterns of codes in the Letters sector of thedisc A therefore will be permitted to pass AND gates 18 for comparisonwith the code signal patterns to be converted; gates 18 being blocked tosignal patterns of codes in the Figures sector 6 as both AND gates 25and 26 will be blocked over the interval codes in sector 6 are passingthe transducer assembly 11.

The output line 21 of the comparator is connected to one leg of each ofeight AND gates 27 and to the set terminal of a flip flop 28 adapted toswitch to set condition in response to the trailing edge of the signalon line 21 for reasons which will hereinafter appear. The other legs ofthe AND gates 27 are connected to associated light responsive celloutput lines 29 of the transducer assembly 12 whereby the code signalpattern detected by the trans-ducer assembly 12 is passed through gates27 during the coincidence interval to bit flop flops in a bufler storageunit 30 thereby storing the 8 bit code pattern 8 corresponding to the 5bit input code pattern on lines 15. The bit output lines 31 of thebufler storage unit are connected to'an OR gate 32 whose output line 33is connected to one of three inputs to a second OR gate 34. The outputof OR gate 34 is connected to the trigger terminal of a one shotmultivibr-ator 35 which responds to the trailing edge of a true signalpassed by OR gate 34. The output signal derived over the active intervalof the multivibrator, which might be incorporated in the reader unitlogic, is connected to the reader command line 14 and its duration needonly be sufficient to assure the initiation of a reader cycle, e.g. aninterval at least equivalent to the pull in time of a cycle clutchmagnet. The trailing edge of the true signal passed by gates 32 and 34coincides with the resetting of the buffer unit 30 whereby the reader iscycled only after data in the buffers has been processed as willhereinafter appear.

The buffer output lines 31 are also each connected to one leg ofassociated AND gates 36. The outputs of the AND gates 27 are also ORedin an OR gate 37 whose output line is connected to the trigger terminalof a one shot precedence delay multivibrator 38 adapted to be triggeredin response to the leading edge of the gate output signal. The output ofthe multivibrator 38 is connected to each of the other input legs of ANDgates 36, thereby to block AND gates 36 over its active interval therebyto provide suflicient time for the processing of a precedence code aswill hereinafter appear. The output lines 39 of the AND gates 36 arealso ORed in an OR gate 41 whose output triggers a process delaymultivibrator 42 whose output is connected to the reset terminal of thebutter unit 30 whereby the latter will reset after the active intervalof the multivibrator 42. The output lines of the AND gates 36 are alsoconnected through OR gates 43 to the bit input lines 44 of aconventional record perforating unit generally designated by reference45. The record perforating unit is one which will reproduce the codepattern on lines 44 in a tape in response to a start process or cycleinitiating clutch signal on a command line 46. The leading edge of thecommand signal may be employed to trigger a one shot delay multivibratorWithin the punch logic which will remain in active state over aninterval suificient to assure the initiation of a punch cycle, e.g. aninterval at least equivalent to the pull in time of a cycle clutchmagnet. The command line 46 is connetced to the output of an OR gate 47having all 8 code lines 44 connected as inputs thereto, so that if anybit is present a process'signal will pass the OR gate 47. The delayprovided by multivibrator 42 is to assure sufiicient time for the punchunit to record the code signal pattern before the butters are reset andconsequently before the reader emits a subsequent code in response tothe resetting of the buffer.

In order that the second system precedence codes may be reproduced theinvention provides a case condition flip flop 49 and upper and lowercase detectors in the form of AND gates 51 and 52 respectively. Eachcase detector gate has three inputs all of which must be true to gate asignal to the gate output lines 53 and 54.

- As noted hereinbefore the output line 21 of the comparator isconnected to flip flop 28 which is adapted to switch from a reset to aset state in response to the trailing edge of the comparator truesignal. The output line 55 of the flip flop is connected to one of theinput legs ofxboth the upper and the lower case AND gates 51 and 52;accordingly when flip flop 28 is set both AND gate inputs connected toline 55 will be true. The output line 56 from the transducer celladapted to sense upper case holes 9 is connected to another input of theupper case AND gate 51 and the output line 57 from the cell positionedto sense the lower case holes is connected to another input of the lowercase AND gate 52. The third input of the upper case AND gate 51 isconnected to one of. the output lines 58 of the case condition flip flop49 and the third input of the lower case AND gate is connected to theother output line 59 of the case condition flip flop. The normal stateeg lower case state, of the case condition flip flop is such that outputline 58 is normally true and output line 59 is normally false.Accordingly, after coincidence, flip flop 28 having been set, only theupper case AND gate 51 will be conditioned; thereby to pass theprecedence or case designator signal generated upon detection of anupper case hole 9 following the code pattern 8 corresponding to thecoincident 5 level code pattern 4. Both cell lines 56 and 57 are ORed inan OR gate 60 whose output is connected to the reset terminal of theflip flop 28 whereby the latter will switch back to reset state on thetrailing edge of the precedence or case designator sensing interval. Theoutput lines 53 and 54 of theAND gates 51 and 52 are connectedrespectively to the set and reset terminals of the case condition flipflop 49 which sets and resets in response to the trailing edge of thesignals passed by the upper case and lower case AND gates respectively.The output lines 53 and 54 of the AND gates 51 and 52 are alsoselectively connected via OR gates 43 to those punch input lines 44which define the upper and lower case precedence codes whereby they maybe processed.

With reference to FIGURE 2, curve 61 represents the output ofmultivibrator 35; curve 62 represents the reader cycle times; curves 63and 64 represent the output of transducer assemblies 11 and 12; curve 65represents the 6 comparator output; curve 66 represents the butteroutput; curve 67 represents the output of the precedence multivibrator;curve 68 represents the output of the process delay multivibrator; curve69 represents the output of flip flop 28; curve 70 represents the outputof either of the AND gates 51 or 52; curve 71 represents the punch cycletimes; and curve 72 represents the state of the case condition flip flop49.

Operation With the discs A and B rotating clockwise, the reader may beinitially cycled by momentarily closing and opening a start switch 73thereby applying a true signal to gate 34. The trailing edge of the gateoutput signal will trigger multivibrator 35 thereby to generate a readercommand signal 74 at time 1 (curve 61). After an interval sufiicient toenable the energization of a cycle clutch magnet the reader will cycleat time t as illustrated by curve 62, generating a bit signal pattern onlines 15 over the sense interval T. During the sense interval T of thereader cycle the dis-cs A and B will have made a complete revolutionsuch that within an interval 1/T beginning e.g., at time t a five bitsignal pattern 4 in the Letters or Figures sector of disc A, as the casemay be, as determined by the last precedence code issued by the readeras hereinbefore explained, will coincide with the signal pattern onlines 15 whereupon the comparator output line 21 will go true over theinterval t -t thereby conditioning gates 27 to pass the corresponding 8bit code pattern 8 sensed simultaneously from disc B over thecoincidence interval t -t and to set the flip flops in the butter unit30 at time t and via OR gate 37 to trigger the precedence delaymultivibrator 38.

The trailing edge of the comparator true signal will set the memory flipflop 28 at time t.;. The switching of the comparator memory flip flop 28to set state applies a true signal via line 55 to upper and lower caseAND gates 51 and 52. As the case condition flip flop 49 is normally in alower case or reset state two of the inputs to the upper case AND gate51 will be true. As the disc B rotates beyond the coincident firstsystem code pattern 8, either an upper or lower case precedence ordesignator. hole 9 or it) will be sensed. If it is a lower case hole 10,indicating that the corresponding character in the second system islower case, the third input (line 56) to the upper case AND gate 51 willremain false so that no signal is passed thereby. Hence the casecondition flip flop 49 will remain in reset state. The lower case ANDgate 52 likewise will not pass a signal as its input connected to thecase condition flip flop output line 59 will be false. The detectedprecedence or case designator signal on line 57 will however pass ORgate 60 thereby resetting the flip flop 28 at the end of the precedencesensing interval i.e. time t thereby to block gates 51 and 52 so thatprecedence or case designator holes sensed prior to the next coincidentcode will not be passed and thereby generate spurious precedence codesor switch the case condition flip flop.

Since neither of the AND gates 51 or 52 pass a signal the punch will notbe cycled during the precedence interval 1 -1 While the precedencemultivibrator 38 is active, gates 36 cannot pass the bit signals storedin the butter 30. At i however, the AND gates 36 pass the bit signalpattern to lines 39 and to the punch input lines 44 thereby setting upselected punch magnets. The perforator unit 45 in response to thecommand signal from OR gate 47, also generated at time i will after apredetermined interval, initiate a punch cycle at time t whereby thecode signal pattern will be recorded in and a record indexed over theinterval t -l As hereinbefore noted the buffer flip flops will be resetafter a delay initiated by process multivibrator 42 which is triggeredat time by the leading edge of the signal pass by OR gate 41 resultingfrom passage of bits signals through AND gates 36; the delay beingprovided to give the record perforator suflicient time to reproduce thedata and index the record tape. As shown in FIGURE 2 (curve 68), thedelay multivibrator 42 remains active until the end of the punch cycleat time i Accordingly the buffers will be reset at time t and thetrailing edge of the signal from OR gates 32 and 34, which is true overthe storage interval, will trigger the multivibrator 35 at time tthereby to initiate another cycle of the reader at time t If an uppercase precedence hole 9 is sensed after the next coincidence interval,illustrated as occurring at time t the memory flip flop 28 being set inresponse to the trailing edge thereof at time r all three inputs to theupper case AND gate will be true at time t and the output of the gate 51will remain true over the precedence sensing interval i -r The trailingedge of the AND gate output signal will set the case flip flop to uppercase state at time t The gated precedence signal on line 53 is connectedto selected bit lines 44 which define the second system upper caseprecedence code pattern thereby setting up punch magnets and via OR gate47 initiating a punch cycle as before, over the interval -1 The leadingedge of the bit signals passed by gates 27 will via OR gate 37 triggerthe precedence delay multivibrator 38 at time t thereby blocking andmaintaining AND gates 36 blocked over the interval sufficient for theprecedence code to be reproduced; the interval being set to terminatecoincidentally with the termination of the punch cycle at time t Asbefore the second system code pattern 8 correspond ing to the coincidentfirst system pattern 4 will be set into the buffer flip flops at time tAs shown in FIGURE 2 when the precedence delay multivibrator returns toquiescent state at t the AND gates 36 will open to pass the signal inthe buffers to lines 39 and to the punch input lines 44; the signals onlines 39 via OR gate 41 triggering the process multivibrator 42 at timer As before the punch will be cycled at a predetermined time thereafteri.e. at a time to record the second system code pattern over theinterval t t after which, the buffers having been reset, another readercycle may be initiated at a time As is evident from FIGURE 2 (curve 66)the buffer unit always remains set over the intervals of bothmultivibrators 38 and 42.

The case condition flip flop 49 will remain in set state untilcoincidence of a first system code which is lower case in the secondsystem. In this event AND gate 52 will pass a sign-a1 which will resetthe case condition flip flop 49 and effect the processing of a lowercase precedence code pattern during the interval of multivibrator 38 andthe processing of the second system pattern corresponding to thecoincident first system code pattern during the active interval ofmultivibrator 42 in the same sequence as when upper case AND gate 51passed a signal.

When a blank is emitted by the reader, no blank code being prerecordedon disc A, it is detected by a blank detector 75 whose output line 76 isconnected to OR circuit 47. This will cycle the record perforating unit45 which, since no code pattern is on lines 44, will simply index tape.The output of the blank detector is also connected to an OR gate 77whose output line 78 is connected to an input of OR gate 34 whereby thetrailing edge of the blank detector true signal will cause themultivibrator 35 to be triggered. As noted hereinbefore the outputsignal of the multivibrator 35 will initiate another reader cycle.

If a 5 level upper or lower case precedence code is issued by thereader, no corresponding codes being recorded on a disc A, they aredetected in associated detectors 22 and 23 as hereinbefore noted andwhose outputs are also ORed in OR gate 77 thereby to effect a subsequentreader cycle.

It should be understood that the foregoing disclosure relates to only apreferred embodiment of the invention and that it is intended to coverall changes and modifications of the example of the invention hereinchosen for the purposes of the disclosure which do not constitutedepartures from the spirit and scope of the invention.

The invention claimed is:

1. Apparatus for converting code patterns of a first system intocorresponding code patterns of a second system wherein code patterns ineach system may be employed twice to represent upper and lower caseinformation, said dual means code patterns being distinguishable bylower and upper case precedence code patterns designating that codepatterns following a precedence code pattern represent lower or uppercase information, and wherein information assigned to upper and lowercase is likely to differ from system to system comprising:

a first disc having serially recorded therein on radial lines firstsystem code patterns,

a second disc having serially recorded therein on radial lines all ofcorresponding ones of second system code patterns and designators of thecase of the information represented thereby, the radial line nextfollowing each radial line bearing a second system code pattern havingrecorded therein the designator of the case of the informationrepresented by the preceding code pattern, the code patterns in saidfirst and second discs representing the same information beingorientated at the same angular positions with respect to a reference oneach of said discs,

a continuously driven shaft,

means mounting said discs with said references in alignment on saidshaft,

first and second transducer means associated with said first and seconddiscs respectively, said transducer means being positioned tosimultaneously read corresponding code patterns and case designatorsthereby generating code signal patterns and case designator signals assaid discs are driven,

a source operative to issue first system code signal patterns,

means to compare for coincidence first system code signal patternsgenerated by said first transducer means and a first system code signalpattern issuing from said source and to generate an output signal overthe interval of coincidence of said first system code signal patterns,

first gate means conditioned by said output signal for passing thesecond system code signal pattern generated by said second transducermeans during the interval of coincidence of first system code signalpatterns,

a buffer unit for storing code signal patterns passed by said first gatemeans,

means for recording second system code signal patterns,

second gate means normally conditioned to pass stored second system codesignal patterns to said recording means,

first delay means being responsive to code signal patterns passedthrough said first gate means for blocking said second gate means overan interval necessary to generate and record a second system precedencecode signal pattern,

second delay means responsive to code signal patterns gated by saidsecond gate means for resetting said buffer unit after an intervalsufficient to record the code signal patterns passed by said second gatemeans,

means operative on said source in response to the resetting of saidbuffer to cause another first system code signal pattern to issuetherefrom,

and means responsive to said output signal and to a designator signalgenerated by said second transducer means following the coincidenceinterval which differs from the designator signal generated by saidsecond transducer means following the previous coincidence interval forgenerating a precedence code signal pattern for recording during saidfirst delay interval.

2. Apparatus as recited in claim 1 wherein said last named meanscomprises a memory flip flop operable to set state in response to thetrailing edge of said output signal,

an upper and a lower case gate conditioned for operation by said setmemory flip flop,

a case condition flip flop operable in reset state to condition thelower and block the upper of said case gates and in set state to blocksaid lower and condition the upper of said case gates, said casecondition flip flop being settable and resettable in response to thetrailing edge of the output signals from said lower and upper case gatesrespectively,

means responsive to the output signal of said lower case gate forgenerating a lower case precedence code signal pattern,

means responsive to the output signal of said upper case gate forgenerating an upper case precedence code signal pattern,

and means connecting upper case designator signals generated by saidsecond transducer means to said upper case gate for passage thereby whensaid case condition flip flop is in reset state and lower casedesignator signals generated by said second transducer means to saidlower case gate for passage thereby when said case condition flip flopis in set state, the trailing edge of said gate designator signalsresettting said memory flip flop.

3. Apparatus as recited in claim 1 further comprising .means responsiveto source issued code signal patterns not prerecorded on said first discfor directing said source to generate a subsequent code signal patternfor conver- SlOIl.

4. Apparatus as recited in claim 1 wherein each code pattern recorded onsaid first disc includes on the same radial line a case designator ofthe information represented by the code pattern, said apparatus furthercompristhird and fourth gate means operable when conditioned to passrespectively lower and upper case designator signals generated by saidfirst transducer means,

a bistable circuit operable to set and reset state in response to sourceissued lower and upper case precedence code signal patterns respectivelyand operable in set and reset states respectively to condition saidthird and fourth gates,

and fifth gate means condtioned by the signals passed by either of saidthird and fourth gate means for passing to said comparing means codesignal patterns generated by said first transducer means whose casedesignator corresponds to the last source issued precedence code signalpattern.

No references cited.

DARYL W. COOK, Acting Primary Examiner. A. L. NEWMAN, AssistantExaminer.

1. APPARATUS FOR CONVERTING CODE PATTERNS OF A FIRST SYSTEM INTOCORRESPONDING CODE PATTERNS OF A SECOND SYSTEM WHEREIN CODE PATTERNS INEACH SYSTEM MAY BE EMPLOYED TWICE TO REPRESENT UPPER AND LOWER CASEINFORMATION, SAID DUAL MEANS CODE PATTERNS BEING DISTINGUISHABLE BYLOWER AND UPPER CASE PRECEDENCE CODE PATTERNS DESIGNATING THAT CODEPATTERNS FOLLOWING A PRECEDENCE CODE PATTERN REPRESENT LOWER OR UPPERCASE INFORMATION, AND WHEREIN INFORMATION ASSIGNED TO UPPER AND LOWERCASE IS LIKELY TO DIFFER FROM SYSTEM TO SYSTEM COMPRISING: A FIRST DISCHAVING SERIALLY RECORDED THEREIN ON RADIAL LINES FIRST SYSTEM CODEPATTERNS, A SECOND DISC HAVING SERIALLY RECORDED THEREIN ON RADIAL LINESALL OF CORRESPONDING ONES OF SECOND SYSTEM CODE PATTERNS AND DESIGNATORSOF THE CASE OF THE INFORMATION REPRESENTED THEREBY, THE RADIAL LINE NEXTFOLLOWING EACH RADIAL LINE BEARING A SECOND SYSTEM CODE PATTERN HAVINGRECORDED THEREIN THE DESIGNATOR OF THE CASE OF THE INFORMATIONREPRESENTED BY THE PRECEDING CODE PATTERN, THE CODE PATTERNS IN SAIDFIRST AND SECOND DISCS REPRESENTING THE SAME INFORMATION BEINGORIENTATED AT THE SAME ANGULAR POSITIONS WITH RESPECT TO A REFERENCE ONEACH OF SAID DISCS, A CONTINUOUSLY DRIVEN SHAFT, MEANS MOUNTING SAIDDISCS WITH SAID REFERENCES IN ALIGNMENT ON SAID SHAFT, FIRST AND SECONDTRANSDUCER MEANS ASSOCIATED WITH SAID FIRST AND SECOND DISCSRESPECTIVELY, SAID TRANSDUCER MEANS BEING POSITIONED TO SIMULTANEOUSLYREAD CORRESPONDING CODE PATTERNS AND CASE DESIGNATORS THEREBY GENERATINGCODE SIGNAL PATTERNS AND CASE DESIGNATOR SIGNALS AS SAID DISCS AREDRIVEN, A SOURCE OPERATIVE TO ISSUE FIRST SYSTEM CODE SIGNAL PATTERNS,MEANS TO COMPARE FOR COINCIDENCE FIRST SYSTEM CODE SIGNAL PATTERNSGENERATED BY SAID FIRST TRANSDUCER MEANS AND A FIRST SYSTEM CODE SIGNALPATTERN ISSUING FROM SAID SOURCE AND TO GENERATE AN OUTPUT SIGNAL OVERTHE INTERVAL OF COINCIDENCE OF SAID FIRST SYSTEM CODE SIGNAL PATTERNS,FIRST GATE MEANS CONDITIONED BY SAID OUTPUT SIGNAL FOR PASSING THESECOND SYSTEM CODE SIGNAL PATTERN GENERATED BY SAID SECOND TRANSDUCERMEANS DURING THE INTERVAL OF COINCIDENCE OF FIRST SYSTEM CODE SIGNALPATTERNS, A BUFFER UNIT FOR STORING CODE SIGNAL PATTERNS PASSED BY SAIDFIRST GATE MEANS, MEANS FOR RECORDING SECOND SYSTEM CODE SIGNALPATTERNS, SECOND GATE MEANS NORMALLY CONDITIONED TO PASS STORED SECONDSYSTEM CODE SIGNAL PATTERNS TO SAID RECORDING MEANS, FIRST DELAY MEANSBEING RESPONSIVE TO CODE SIGNAL PATTERNS PASSED THROUGH SAID FIRST GATEMEANS FOR BLOCKING SAID SECOND GATE MEANS OVER AN INTERVAL NECESSARY TOGENERATE AND RECORD A SECOND SYSTEM PRECEDENCE CODE SIGNAL PATTERN,SECOND DELAY MEANS RESPONSIVE TO CODE SIGNAL PATTERNS GATED BY SAIDSECOND GATE MEANS FOR RESETTING SAID BUFFER UNIT AFTER AN INTERVALSUFFICIENT TO RECORD THE CODE SIGNAL PATTERNS PASSED BY SAID SECOND GATEMEANS, MEANS OPERATIVE ON SAID SOURCE IN RESPONSE TO THE RESETTING OFSAID BUFFER TO CAUSE AWNOTHER FIRST SYSTEM CODE SIGNAL PATTERN TO ISSUETHEREFROM, AND MEANS RESPONSIVE TO SAID OUTPUT SIGNAL AND TO ADESIGNATOR SIGNAL GENERATED BY SAID SECOND TRANSDUCER MEANS FOLLOWINGTHE COINCIDENCE INTERVAL WHICH DIFFERS FROM THE DESIGNATOR SIGNALGENERATED BY SAID SECOND TRANSDUCER MEANS FOLLOWING THE PREVIOUSCOINCIDENCE INTERVAL FOR GENERATING A PRECEDENCE CODE SIGNAL PATTERN FORRECORDING DURING SAID FIRST DELAY INTERVAL.